1. Field of the Invention
The present invention relates to a high speed visual information processing device comprising both an image sensor section capable of sensing a visual image and a neural information processing section adapted to perform parallel processing on a visual image signal and which is capable of parallel transfer of a visual image signal from the image sensor section to the neural information processing section.
2. Prior Art
FIG. 1 is a block diagram showing a general construction of a conventional visual information processing system. In the drawing, an image signal sensor section 1 and an image signal processing section 3 are connected to each other through an image signal transmission section 2. The image signal carries two-dimensional information in the X- and Y-directions. In the case of a moving image wherein information changes with passage of time, image signals entered to respective pixels of the image sensor section 1 have to be read out at a fixed period before they are transmitted to the image signal processing section 3. Given the number of pixels contained in image signals and the type of signal processing method, signal processing speed of this visual information processing system are determined by the following factors:
(1) The speed at which all (x, y) signals are written to the image sensor section (the speed of response); PA1 (2) The speed at which the signals having been written to the image sensor section are read out; PA1 (3) The speed at which the transmitted signals are written to the signal processing section; and PA1 (4) The speed at which signals are processed in the signal processing section.
Thus, with an above-described type of visual information processing system which employs silicon CCDs as the image sensor and a serial arithmetic CPU as the signal processing section, transmission and processing of signals are very slow due to the serial processing, so that, in many cases, it may be impossible to effect a real time pattern recognition (of visual information processing within a period of about 30 msec).
FIG. 2 shows a three-dimensional resistor network for optical flow calculation shown, for example, on page 101 of "Neural Computers" by K. Koch, et al. (Berlin, 1988). In the drawing, the reference numeral 4 indicates an equivalent circuit simulating a photovoltaic device, such as a photodiode, irradiated with light. This equivalent circuit 4 includes a voltage source 5 and a capacitor 6, and a resistor 7 both present in the equivalent circuit. The reference numerals 8 and 9 indicate upper and lower contacts in the three-dimensional resistor network; 10 indicates a resistor connecting the upper and lower contacts 8 and 9 to each other; 11 indicates resistors interconnecting the contacts 8 in the upper layer and the contacts 9 in the lower layer; and 12 indicates switches provided in these resistors 11.
The operation of this resistor network will be described. Visual information on an object obtained from the photodiode is simultaneously supplied to the contacts of the three-dimensional resistor network at fixed time intervals. A movement of the object causes a change in the light signal, thereby causing changes in voltage at the contacts 8 and 9. Thus, the network system, which has been stable, is disturbed to proceed to a new phase of stability. From the values of voltage at the contacts 8 and 9 which have attained a stable condition, two-dimensional velocity vectors in the X- and Y-directions can be obtained. The switches 12 prevent the contour of the object in the image from being blurred in this process, allowing the contour to be formed at reasonable positions.
Regarding the conventional visual image information processing device being constructed such as described above, it is quite difficult to form an image sensor section, such as a photodiode, and an image signal processing section in one and the same device so as to effect a parallel transmission of image signals. Further, it is difficult to build up a three-dimensional resistor network, such as an optical flow, within a conventional semiconductor device.